The integrated circuit technology has a need to obtain narrow line widths in the range of 1 micrometer or less by extending standard photolithography techniques and avoiding the need to use the more expensive and complex techniques such as electron beam or X-ray lithography. One such technique is described in H. B. Pogge in IBM Technical Disclosure Bulletin, November 1976, Vol. 19, No. 6, pp. 2057-2058, entitled "Narrow Line Widths Masking Method". This method involves the use of a porous silicon followed by the oxidation of the porous silicon. Another technique described by S. A. Abbas et al. in the IBM Technical Disclosure Bulletin, Vol. 20, No. 4, September 1977, pp. 1376-1378. This method describes the use of polycrystalline silicon masking layers which are made into a mask by first using an intermediate mask of oxidation blocking material, such as silicon nitride in the formation of polycrystalline silicon. Line dimensions below about 2 micrometers may be obtained by this technique.
U.S. Pat. Nos. 4,209,349 and 4,209,350 by I. T. Ho et al., U.S. Pat. No. 4,234,362 by J. Riseman and U.S. Pat. No. 4,256,514 by H. B. Pogge describe methods for forming narrow dimensioned, for example, sub-micrometer regions on a silicon body. These patents all involve the formation of substantially horizontal surfaces and substantially vertical surfaces on a silicon body and then forming a layer of a very narrow dimension on both the substantially horizontal and substantially vertical surfaces. This layer is then subjected to an anisotropic etching process such as by reactive ion etching, to substantially remove the horizontal layer while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending upon the original thickness of the layer applied. In this way such a narrow dimension region as 1 micrometer or less is obtained.
There has been significant effort in the integrated circuit field to develop processes for making sub-micrometer channel length field effect transistors with a high degree of channel length control. Examples of this work are described in "A New Edge-defined Approach for Sub-micrometer MOSFET Fabrication" by W. R. Hunter et al., IEEE Electron Device Letters, Vol. EDL-2 No. 1, January 1981, pp. 4-6, "Sub-micrometer Polysilicon Gate CMOS/SOS Technology"by A. C. Ipri et al. published in IEEE Transactions on Electron Devices, Vol. ED-27, No. 7, July 1980, pp. 1275-1279 and "A Novel Sub-micron Fabrication Technique" by T. N. Jackson et al. published in IEDM 1979 Conference Volume, pp. 58-61. The first paper relies on the reactive ion etching technique to form a sidewall silicon dioxide. The second paper utilizes a technique involving lateral diffusion of boron. The third method uses the plating of a metal on the edge of a conventionally patterned metal layer. Other short channel field effect transistor devices are illustrated in the W. E. Armstrong U.S. Pat. No. 4,062,699; J. Goel U.S. Pat. No. 4,145,459 and J. H. Scott, Jr. U.S. Pat. No. 4,201,603. The Armstrong patent utilizes an ion implantation and diffusion process to narrow the channel length of his MOSFET. The Goel patent utilizes a process sequence that involves the use of a recess formed in the portion of the semiconductor body and further involves the plating of metal films on each side of the recess until the spacing between the metal film across the recess is equal to desired length of the gate. The Scott, Jr. patent controllably doped an edge of polysilicon layer and then is able to remove the undoped polysilicon by etching it with a material which does not etch the doped polysilicon region.
U.S. Pat. No. 4,319,932 to C. G. Jambotkar; pending patent application Ser. No. 167,184 filed July 8, 1980 by G. R. Goth, I. E. Magdo and S. D. Malaviya; and U.S. Pat. No. 4,322,883 to S. A. Abbas and I. E. Magdo relate to the fabrication of bipolar integrated circuit structures and devices which have contacts to the elements of the devices in close proximity to one another and in self-aligned manner. The G. R. Goth et al. patent application and S. A. Abbas et al patent describe self-aligned metal processes which achieve self-aligned metal silicon contacts and micron to sub-micron contact-to-contact and metal-to-metal spacing by use of a pattern of dielectric material having a thickness of the order of a micron or less. The C. G. Jambotkar patent employs a doped polycrystalline silicon base contact formed close to the emitter openings in a self-aligned manner wherein the isolation between the base contact and emitter contact is a layer of thermally grown silicon dioxide on the surface of the polycrystalline silicon base contact. U.S. Pat. No. 4,359,816 to S. A. Abbas and I. E. Magdo describe a related process and resulting integrated circuit structure which involves the formation of field effect transistors which achieve self-aligned metal or polycrystalline silicon contacts and micron-to-sub-micron contact-to-contact and metal-to-metal spacing by use of a pattern of dielectric material having a thickness of the order of a micron or less.
It is desirable to provide a high density integrated circuit device structure whether the devices are bipolar or field effect transistors that is useful in memory or logic. It is also useful to have the processing to be as simple as possible. The self-aligned recessed oxide isolation to the device areas is also important in reducing the spacing between devices which in turn increases the density of devices within an integrated circuit.